Application-Specific Heterogeneous Network-on-Chip Design

As a result of increasing communication demands, application-specific and scalable Network-onChips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor Systemon-Chips. A challenge in application-specific NoC design is to find the right balance among different tradeoffs, such as communication latency, power consumption and chip area. We propose a novel approach that generates latency-aware heterogeneous NoC topology. Experimental results show that our approach improves the total communication latency up to 27% with modest power consumption.